1. Technical Field
The present invention relates to a non-volatile memory device, and more particularly, to a resistance random access memory device and a phase change random access memory device.
2. Related Art
With recent brilliant development of the information communication industry, a need for various memory devices has increased. Particularly, memory devices for mobile terminals and MP3 players require a non-volatile property that written data is not erased even when it is turned off. Since the non-volatile memory devices can electrically store and erase data and can store data even with no power, applications thereof have increased in various fields. However, a known dynamic random access memory (DRAM) formed of semiconductor has a volatile property that stored information is erased with no power, and thus non-volatile memory devices to be replaced for the DRAM have been studied.
As a representative non-volatile memory device, a flash memory device having an electrically-isolated floating gate was actively studied in the past. However, a magnetic RAM (MRAM) using a magnetic resistance changing phenomenon, a ferroelectric RAM (FRAM) using a spontaneous polarization phenomenon of ferroelectrics, a resistance RAM (ReRAM) using a resistance switching or conductivity switching phenomenon of a metal oxide film, and a phase change RAM (PRAM) using a phase change phenomenon were studied as the non-volatile memory devices in recent years. Particularly, the resistance random access memory and the phase change random access memory have a relatively simple structure and a relatively simple manufacturing process in comparison with the other non-volatile memory devices and thus have attracted much attention.
The resistance RAM exhibits a characteristic that oxide is switched from a high resistance state (HRS) to a low resistance state (LRS) when an electrical signal is applied to a basic element structure of metal-oxide-metal. The oxide is switched from the LRS to the HRS with another electrical signal. It is called “set” that the oxide is switched from the HRS to the LRS. On the contrary, it is called “reset” that the oxide is switched from the LRS to the HRS. The set state means the LRS and the reset state means the HRS. Information is written to and read from the resistance RAM by the use of the switching of resistance.
The phase change RAM includes a transistor and a storage node. The storage node has a structure in which a lower electrode, a phase change layer, and an upper electrode are sequentially stacked and the transistor is used as a switching element. When the phase change layer of the phase change RAM is crystalline, it corresponds to the LRS. When the phase change layer is amorphous, it corresponds to the HRS. It is called “set” that the phase change layer is changed from the HRS to the LRS, that is, that the phase change layer is changed from the amorphous state to the crystalline state. On the contrary, it is called “reset” that the phase change layer is changed from the LRS to the HRS, that is, that the phase change layer is changed from the crystalline state to the amorphous state. As described above, the set state means the LRS and the reset state means the HRS.
When elements exhibiting the resistance switching phenomenon are integrated using a transistor as a switching element like the known DRAM, the resistance RAM has a structure very similar to the phase change RAM. However, because of the deterioration in performance of the transistors with the increase in degree of integration, a cross bar array structure is more preferable than the above-mentioned structure.
The known resistance RAM is shown in FIG. 1A. As shown in FIG. 1A, the known resistance RAM 100 has a structure in which resistance memory elements 140 having a resistance switching layer 120 disposed between electrodes 110 and 130 perpendicular to each other are arranged in a matrix. For example, information of “1” and “0” is stored depending on the resistance state of the resistance switching layer 120 of each resistance memory element 140, that is, the LRS and the HRS, respectively.
The writing and reading of information to and from the resistance memory element 140 will be described now. In order to write information to a selected resistance memory element 140, voltages for switching the resistance switching layer 120 to the LRS or the HRS are applied to the electrodes 110 and 130 of the selected resistance memory element 140. In order to read information therefrom, reading voltages are applied to the electrodes 110 and 130 of the selected resistance memory element 140 and current flowing in one electrode 110 or 130 is measured. That is, when the magnitude of current is relatively great, it corresponds to “1” as the LRS. When the magnitude of current is relatively small, it corresponds to “0” as the HRS.
When information is read from the resistance Ram 100, there is a problem that the information is influenced by the resistance state of the resistance switching layer of another resistance memory element in addition to the resistance state of the resistance switching layer 120 of the resistance memory element 140 selected to read information therefrom. Such a problem is shown in FIG. 1B.
The reading of information from the resistance memory element 151 having the resistance switching layer 121 in the HRS will be described now. In order to read information, a reading voltage should be applied across the electrodes 111 and 131 of the selected resistance memory element 151. For example, 0 V as a reference voltage is applied to the electrode 111 and Vread as a reading voltage is applied to the electrode 131. Current flows in the direction of an arrow 170 and information is read by measuring the value of the current. When the resistance switching layer 121 of the selected resistance memory element 151 is in the HRS, the measured current value should be relatively small, which can be said that the information is correctly read.
When the voltages are applied in the above-mentioned method, current also flows in the direction of an arrow 180, in addition to the arrow 170. In this case, as shown in FIG. 1B, when the resistance switching layers 122, 123, and 124 of the peripheral resistance memory elements 152, 153, and 154 are in the LRS, the value of current flowing in the direction of the arrow 180 is greater than the value of current flowing in the direction of the arrow 170. Accordingly, the resistance switching layer 121 of the selected resistance memory element 151 is in the HRS but the relatively great value of current may be measured to read the information as the LRS.
Similarly to the resistance RAM, the above-mentioned problem with the erroneous reading of information occurs in the phase change RAM.